High performance and reduced power consumption are important factors for semiconductor devices, especially for mobile applications, various integrated circuit (IC) components, power gating has emerged as a technique for mitigating subthreshold leakage in low threshold voltage transistors, logic blocks, circuits, and other devices. In a power gated configuration, groups of transistors, logic blocks, circuits, etc, may be selectively coupled and decoupled from a power supply. In this way, the specific groups of transistors, logic blocks, circuits, etc. may be selectively provided power on an individual basis, as controlled by a power gating circuit. Typically, the power gating circuit couples each of the groups via low leakage, high threshold voltage switches, such as a complementary metal-oxide-semiconductor (CMOS) switch, controlled by power gating controllers. For example, a low-leakage P-type metal-oxide-semiconductor (PMOS) transistor may be utilized as a header switch to shut off first supply voltage to the parts of a circuit in a standby state, while a low-leakage N-type metal-oxide-semiconductor (NMOS) transistor may be used as a sleep transistor shutting off second supply voltage.